Experimental evaluation of a compiler-based cache energy optimization strategy


Kandemir M., Kolcu I., Kadayif I.

15th Annual IEEE International ASIC/SOC Conference, New-York, United States Of America, 25 - 28 September 2002, pp.296-300 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/asic.2002.1158074
  • City: New-York
  • Country: United States Of America
  • Page Numbers: pp.296-300

Abstract

In this paper, we present experimental results from an optimization strategy that aims at reducing per access energy cost for direct-mapped data caches. We have developed a compiler algorithm that uses access pattern analysis to determine those references that are certain to result in cache hits (called 'certain hits') in a virtually-addressed, direct-mapped data cache. After detecting such references, the compiler substitutes the corresponding load operations with,energy-efficient loads' that access only data array of cache instead of both tag and data arrays. This tag access elimination, in turn, reduces the per access energy consumption for data accesses. Our experimental results indicate that certain hits constitute a large percentage of total hits. They also show that even our most conservative strategy improves the data cache energy consumption by 11% on the average.