Access pattern restructuring for memory energy

De La Luz V., Kadayif I., Kandemir M.

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol.15, no.4, pp.289-303, 2004 (Peer-Reviewed Journal) identifier identifier

  • Publication Type: Article / Article
  • Volume: 15 Issue: 4
  • Publication Date: 2004
  • Doi Number: 10.1109/tpds.2004.1271179
  • Journal Indexes: Science Citation Index Expanded, Scopus
  • Page Numbers: pp.289-303


Improving memory energy consumption of programs that manipulate arrays is an important problem as these codes spend large amounts of energy in accessing off-chip memory. In this-paper, we propose a data-driven strategy to optimize the memory energy consumption in a banked memory system. Our compiler-based strategy modifies the original execution order of loop iterations in array-dominated applications to increase the length of the time period(s) in which memory banks are idle (i.e., not accessed by any loop iteration). To achieve this, it first classifies loop iterations according to their bank accesses patterns and then, with the help of a polyhedral tool, tries to bring the iterations with similar bank access patterns close together. Increasing the idle periods of memory banks brings two major benefits: first, it allows us to place more memory banks into low-power operating modes and, second, it enables us to use a more aggressive (i.e., more energy saving) operating mode (hence, saving more energy) for a given bank (instead of a less aggressive mode). The proposed strategy can reduce memory energy consumption in both sequential and parallel applications. Our strategy has been implemented in an experimental compiler using a polyhedral tool and evaluated using nine array-dominated applications on both a cacheless system and a system with cache memory. Our experimental results indicate that the proposed strategy is very successful in reducing the memory system energy and improves the memory energy by as much as 36.8 percent over a strategy that uses low-power modes without optimizing data access pattern. Our results also show that optimizations that target reducing off-chip memory energy can generate very different results from those that target at improving only cache locality.