Generating physical addresses directly for saving instruction TLB energy

Kadayif I., SIVASUBRAMANIAM A., KANDEMIR M., KANDIRAJU G., CHEN G.

35th Annual IEEE/ACM International Symposium on Microarchitecture, İstanbul, Turkey, 18 - 22 November 2002, pp.185-196 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/micro.2002.1176249
  • City: İstanbul
  • Country: Turkey
  • Page Numbers: pp.185-196
  • Çanakkale Onsekiz Mart University Affiliated: No

Abstract

Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. This paper embarks on a new philosophy for reducing the number of accesses to the instruction TLB (iTLB)for power and performance optimizations. The overall idea is to keep a translation currently being used in a register and avoid going to the iTLB as far as possible - until. there is a. page change. We propose four different approaches for achieving this, and experimentally demonstrate that one of these schemes that uses a combination of compiler and hardware enhancements can reduce iTLB dynamic power by over 85% in most cases.