Optimizing instruction TLB energy using software and hardware techniques


Kadayif I. , SIVASUBRAMANIAM A., KANDEMIR M., KANDIRAJU G., Chen G., Chen G.

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, vol.10, no.2, pp.229-257, 2005 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 10 Issue: 2
  • Publication Date: 2005
  • Doi Number: 10.1145/1059876.1059879
  • Title of Journal : ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
  • Page Numbers: pp.229-257

Abstract

Power consumption and power density for the Translation Look-aside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. After pointing out the importance of instruction TLB (iTLB) power optimization, this article embarks on a new philosophy for reducing the number of accesses to this structure. The overall idea is to keep a translation currently being used in a register and avoid going to the iTLB as far as possible-until there is a page change. We propose four different approaches for achieving this, and experimentally demonstrate that one of these schemes that uses a combination of compiler and hardware enhancements can reduce iTLB dynamic power by over 85% in most cases.