Reducing Performance Impact of Process Variation For Data Caches


8th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 28 - 30 November 2013, pp.380-384 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/eleco.2013.6713866
  • City: Bursa
  • Country: Turkey
  • Page Numbers: pp.380-384
  • Çanakkale Onsekiz Mart University Affiliated: Yes


In concurrent with finer-granular process technologies, it is becoming extremely difficult to keep critical physical device parameters within desired bounds, including channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters can lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices: Different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead for data cache accesses. To overcome varying access latencies across different data cache lines, we employ a small table storing the access latencies of cache lines. This table is accessed during data cache access to give a hint to the hardware about how long to wait for data to become available.