CCC: Crossbar connected caches for reducing energy consumption of on-chip multiprocessors


LI L., VIJAYKRISHNAN N., KANDEMIR M., IRWIN M., Kadayif I.

Euromicro Symposium on Digital System Design, BELEK, Turkey, 1 - 06 September 2003, pp.41-48 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/dsd.2003.1231898
  • City: BELEK
  • Country: Turkey
  • Page Numbers: pp.41-48

Abstract

With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for building complex single processor based architectures, recent trends indicate a shift towards on-chip multiprocessor systems since they are simpler to implement and can provide better performance. An important problem in on-chip multiprocessors is energy consumption. In particular, on-chip cache structures can be major energy consumers. In this work, we study energy behavior of different cache architectures, and propose a new architecture, where processors share a single, banked cache using crossbar interconnects. Our detailed cycle-accurate simulations show that this cache architecture brings energy benefits ranging from 9% to 26% (over an architecture where each processor has a private cache).