An energy saving strategy based on adaptive loop parallelization


39th Design Automation Conference, Louisiana, United States Of America, 10 - 14 June 2002, pp.195-200 identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • City: Louisiana
  • Country: United States Of America
  • Page Numbers: pp.195-200
  • Çanakkale Onsekiz Mart University Affiliated: Yes


In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop in a multi-processor on-a-chip (MPOC) are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67% energy savings with up to 17% performance loss in a set of array-intensive applications. We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut-down and pre-activation can be very effective in reducing energy consumption without increasing execution time.