Instruction compression and encoding for low-power systems


Kadayif I. , KANDEMIR M.

15th Annual IEEE International ASIC/SOC Conference, New-York, United States Of America, 25 - 28 September 2002, pp.301-305 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/asic.2002.1158075
  • City: New-York
  • Country: United States Of America
  • Page Numbers: pp.301-305

Abstract

Low-power system design is very important in battery-operated embedded systems. Since instruction memory constitutes a large portion of the system, it is one of the major energy contributors. In this paper, we propose two selective instruction compression methods for reducing instruction memory and instruction bus energy consumption. In these methods, both compressed and uncompressed instructions are stored in the instruction memory in a mixed fashion. the compressed instructions are decompressed on-the-fly by means of an instruction decode table placed between instruction memory and core. Our methods selectively compress instructions in the sense that while some instances of a given instruction are compressed, some other instances of the same instruction are not. Even though both of the proposed methods can reduce both dynamic and leakage energy consumption in the instruction memory, one of them is more oriented towards reducing dynamic energy, whereas the other one mainly targets leakage. To reduce the instruction bus energy consumption further, we also propose a heuristic method for coding compressed instructions to reduce bit switching on the bus.